1. Field of the Invention
The invention relates to the field of electrically alterable memory devices particularly those employing MOS floating gate structures.
2. Prior Art
Metal-oxide-semiconductor (MOS) floating gate devices are commonly employed in integrated circuit programmable read-only memories (PROMs). Typically, charge is transferred into an electrically isolated (floating) gate to represent one binary state while an uncharged gate represents the other binary state.
Perhaps the earliest reference to a floating gate device is found in U.S. Pat. No. 3,500,142 (Kahng device). In this device, a thin oxide of approximately 50 A separates the entire active channel region from the floating gate. An overlying gate provides capacitive coupling to the floating gate allowing an electric field to be established across this thin oxide. Carriers are tunneled from the channel region into the floating gate to charge the gate. Because of the difficulties in fabricating reliable thin oxides over large areas, this device has never become commercially feasible.
The first commercial floating gate memories employed avalanche injection as a mechanism for transferring charge to the floating gate, thus allowing electrical programming. With the discovery of these FAMOS devices charge could be transported across relatively thick oxides (500 A-1000 A), thereby permitting the reliable fabrication of these devices. Such devices are disclosed in U.S. Pat. No. 3,660,819. Subsequently, "channel injection" again through a relatively thick oxide has been used for programming memory devices. For an example of this type of device see U.S. Pat. No. 3,996,657.
Currently floating gate memories are erased by exposing the array to radiation such as ultraviolet radiation. Numerous structures have been proposed for the erasing by an avalanche mechanism, however, none of these structures have performed very well. An example of one such device is shown in U.S. Pat. No. 3,797,000.
A number of memory devices have been disclosed in which carriers are tunneled through a relatively thick oxide (500 A-1000 A) for both programming and erasing. In some cases, textured gates are employed which provide an enhanced electric field. This field enables tunneling at lower potentials than would otherwise be necessary. One such device is disclosed in U.S. Pat. No. 4,099,196. None of these devices, thus far, have been used in a commercial memory. The device of the present invention is more like the Kahng device shown in U.S. Pat. No. 3,500,142 in that tunneling through a thin oxide is used rather than avalanche injection or channel injection. However, unlike the Kahng device, the thin oxide area constitutes only a small fraction of device area. The reduction of the thin oxide area greatly reduces the fabrication difficulties of the Kahng device where a thin oxide is employed over the entire channel region. Moreover, with the device of the present invention since programming and erasing occurs from an n-type region in the substrate (for an n-channel embodiment) only a positive power supply is required for both programming and erasing.
In IEEE Journal of Solid State Circuits, Vol. SC-12, No. 5, Oct. 1977 (pages 507-514), in an article entitled, "An 8192-Bit Electrically Alterable ROM Emphasizing a One-Transistor Cell with Floating Gate", a cell is described which employs a limited area of 400 A-500 A thick oxide for erasing. This device is programmed by avalanche injection and is reportedly erased by Fowler-Nordheim emission although a field of only 6.5.times.10.sup.6 volts/cm is employed. As shown on Page 509 in FIG. 4, approximately 80 seconds is required for erasing (compared with 1 millisec. for the device of the present invention).
The only electrically erasable integrated circuit PROMs known to the applicant which are used in large quantities are those employing silicon nitride layers. These devices have shorter retention times than floating gate devices and in many cases they require both a positive and negative power supply. In some instances, only a single supply is required. However, in these cases, the memory cell area is substantially more than is required for memory cells fabricated in accordance with the present invention.